1. Technical Field
Various embodiments relate generally to an electronic circuit and, more particularly, to a semiconductor memory device.
2. Related Art
An internal circuit included in a semiconductor memory device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The semiconductor memory device is designed such that bulk voltages are applied to the bulk terminals of the PMOS transistors and the NMOS transistors. This is to prevent the occurrence of a latch-up phenomenon and prevent the threshold voltages of the MOS transistors from being unstably changed by a body effect.
In general, the levels of the bulk voltages applied to PMOS transistors and NMOS transistors exert influences on the leakage current of the PMOS transistors and the NMOS transistors which are in a turned-off state and on the operation speeds of the PMOS transistors and the NMOS transistors which are in a turned-on state. That is to say, in the case of an NMOS transistor, as a bulk voltage with a level lower than the voltage of a source terminal is applied, the amount of leakage current and an operation speed are decreased. Further, in the case of a PMOS transistor, as a bulk voltage with a level higher than the voltage of a source terminal is applied, the amount of leakage current and an operation speed are decreased.
Additionally, a semiconductor memory device has a power-down mode as one of standby modes. The power-down mode is an operation mode in which, although power is applied, the generation of an internal clock is interrupted to reduce power consumption. In the power-down mode, it is important that the amount of leakage current is limited to a minimum to reduce power consumption. Therefore, in the power-down mode, it is advantageous in terms of reduction of power consumption to set lower the level of the bulk voltage of an NMOS transistor and set higher the level of the bulk voltage of a PMOS transistor.